The UT-Ethernut Interface adds Ethernet connectivity to the parallel
bus system designed for the Raizen lab at the University of Texas.
The system is comprised of an embedded Ethernut
computer and an interface circuit with FIFOs and a clock input. Data is
loaded into memory over TCP/IP and then clocked onto the parallel bus
from the Ethernut's memory, through the FIFO buffers. We have
some pictures of an assembled
Manual (in progress)
Design Works File of
Rev. 4 interface circuit, from which the schematic was made (dsw)
Schematic of Rev. 4 interface circuit (pdf)
Osmond Quartz File of
Rev. 4 interface circuit board layout (osm)
Gerber Files of
Rev. 4 interface circuit board layout (zip)
PostScript Files of
Rev. 4 interface circuit board layout, roughly equivalent to the
above Gerber files (zip)
generated from the above Gerber files (zip)
Source Code for
Ethernuts running an interface circuit (zip). Needs Nut/OS to be compiled.
This can be unzipped directly into the application tree once Nut/OS is installed.
Includes working code for Digital Output boxes (with two Digital
Output circuits) and Analog Output boxes (with two Analog Output
Library files for
communicating with Ethernuts running interface circuits (zip).
Includes a sample program and some utilities. The library and sample
programs are all written in Perl.
These are interface circuits from the Raizen Lab:
Circuit manual, including schematics (pdf). This file was
Digital Output Circuit
manual, including schematics (pdf). This file was originally here.
DDS Circuit manual, including
schematics (pdf). This file was originally here.